FIG. 14 is a circuit diagram of an input-output circuit in a conventional semiconductor integrated circuit with a signal level converting function. The signal level converting function in such a semiconductor integrated circuit means the following two functions.
(1) Converting the level of signal voltage issued from an internal circuit operated at a supply voltage of the semiconductor integrated circuit, and supplying the newly obtained voltage to an external circuit operated at a supply voltage different from this supply voltage (that is, an internal circuit of other semiconductor integrated circuit); and
(2) Converting the level of signal voltage received from an external circuit operated at a supply voltage different from the supply voltage of the semiconductor integrated circuit, and supplying the newly obtained voltage to an internal circuit.
The input-output circuit shown in FIG. 14 includes an output buffer circuit 12h, an electrostatic protective circuit 8, and an input buffer circuit 9. As shown in FIG. 14, theoutput buffer circuit 12h is composed of an input circuit unit 10h and an output circuit unit 11h. The input circuit unit 10h is classified into a circuit unit operated at a first supply potential VDD1 and a circuit unit operated at a second supply potential VDD2.
As shown in FIG. 14, the input circuit unit 10h is divided into two sections of a first signal processing unit and a second signal processing unit. The first signal processing unit receives a data input signal IN1 issued from the internal circuit into an input terminal 1 and processes this data input signal IN1. The second signal processing unit receives an output control signal IN2 issued from the internal circuit into a control terminal 2 and processes this output control signal IN2.
The first signal processing unit is composed of a PMOS transistor MP111, an NMOS transistor MN111, a PMOS transistor MP112, an NMOS transistor MN112, and an inverter G111. The PMOS transistor MP111 has its source connected to the second supply potential VDD2. The NMOS transistor MN111 has its source connected to the grounding potential GND, drain connected to the drain of the PMOS transistor MP111 and gate connected to the input terminal 1. The PMOS transistor MP112 has its source connected to the second supply potential VDD2, and gate connected to the drain of the NMOS transistor MN111. The NMOS transistor MN112 has its drain connected to the gate of the PMOS transistor MP111 and the drain of the PMOS transistor MP112. The input terminal of the inverter G111 is connected to the input terminal 1 and the output terminal is connected to the gate of the NMOS transistor MN112. The point where the gate of the PMOS transistor MP111, the drain of the PMOS transistor MP112, and the drain of the NMOS transistor MN112 are connected to each other will be referred to as node N111.
Thus, the first signal processing unit is a circuit which converts the level of the data input signal IN1 received from the internal circuit and supplies the newly obtained signal to the node N111.
On the other hand, the second signal processing unit is composed of a PMOS transistor MP113, an NMOS transistor MN113, a PMOS transistor MP114, an NMOS transistor MN114, and an inverter G112. The PMOS transistor MP113 has its source connected to the second supply potential VDD2. The NMOS transistor MN113 has its source connected to the grounding potential GND, drain connected to the drain of the PMOS transistor MP113 and gate connected to the control terminal 2. The PMOS transistor MP114 has its source connected to the second supply potential VDD2, and gate connected to the drain of the NMOS transistor MN113. The NMOS transistor MN114 has its drain connected to the gate of the PMOS transistor MP113 and the drain of the PMOS transistor MP114. The input terminal of the inverter G112 is connected to the control terminal 2 and the output terminal is connected to the gate of the NMOS transistor MN114. The point where the gate of the PMOS transistor MP113, the drain of the PMOS transistor MP114, and the drain of the NMOS transistor MN114 are connected to each other will be referred to as node N112.
Thus, the second signal processing unit is a circuit which converts the level of the output control signal IN2 received from the internal circuit and supplies the newly obtained signal to node N112.
In particular, the first and second signal processing units operate, supposing the operating voltage of the internal circuit to be first supply potential VDD1, as a latch signal level converting circuit which converts the level of the signal of the first supply potential VDD1 level into a signal of the second supply potential VDD2 level.
As mentioned above, the input circuit unit 10h is divided into a circuit which operates at the first supply potential VDD1 and a circuit which operates at the second supply potential VDD2. The former circuit comprises the inverters G111 and G112. The latter circuit comprises the PMOS transistors MP111 and MP112, NMOS transistors MN111 and MN112, PMOS transistors MP113 and MP114, and NMOS transistors MN113 and MN114.
In FIG. 14, the symbol "VDD1.rarw." indicates the circuit that operates at the first supply potential VDD1 which is the supply voltage of the internal circuit. On the other hand, and the symbol ".fwdarw.VDD2" indicates the circuit that operates at the second supply potential VDD2. Although the internal circuit is not shown in this diagram, this internal circuit operates at the first supply potential VDD1. Further, an output circuit unit 11h, which will be explained below, operates at the second supply potential VDD2. It is assumed here that a relation of VDD2&gt;VDD1&gt;GND holds.
The output circuit unit 11h is composed of an inverter G113, a two-input NAND gate G114, a two-input NOR gate G115, a PMOS transistor MP115, and an NMOS transistor MN115. The inverter G113 has its input terminal connected to the node N112. The two-input NAND gate G114 has one of its input terminals connected to the node N111 and the other input terminal connected to the output terminal of the inverter G113. The two-input NOR gate G115 has one of its input terminals connected to the node N111 and the other input terminal connected to the node N112. The PMOS transistor MP115 has its source connected to the second supply potential VDD2 and gate connected to the output terminal (node N114) of the NAND gate G114. The NMOS transistor MN115 has its drain connected to the drain of the PMOS transistor MP115, its source connected to the grounding potential GND, and its gate connected to the output terminal (node N115) of the NOR gate G115. This output circuit unit 11h operates on the second supply potential VDD2.
The gate insulating film of the MOS transistors which compose the PMOS transistors MP111 to MP115, NMOS transistors MN111 to MN115, inverter G113, NAND gate G114, and NOR gate G115 is thicker than the gate insulating film of the MOS transistors which compose the inverters G111 and G112. Such an arrangement is provided in order to prevent damage of the gate insulating films of these MOS transistors.
The electrostatic protective circuit 8 is connected to the input-output terminal 3 (PAD terminal). This electrostatic protective circuit 8 functions to protect the output buffer circuit 12h from electrostatic breakdown in the following manner. That is, when an input signal of high potential is input from the input-output terminal 3 the electrostatic protective circuit 8 establishes a low impedance state, on the other hand, when an input signal of low potential or operating voltage is input the electrostatic protective circuit 8 establishes a high impedance state. This electrostatic protective circuit 8 is formed by combining a junction diode, a diffusion region, and a resistance element using a polysilicon layer on a substrate.
The input buffer circuit 9 comprises a circuit converts the signal level of an external input signal having the H level and L level defined by the second supply potential VDD2 and grounding potential GND into signals having the H level and L level defined by the first supply potential VDD1 and grounding voltage GND. The input buffer circuit 9 also comprises an input driver circuit.
As mentioned above, the semiconductor integrated circuit shown in FIG. 14 is a circuit which transmits a signal from an internal circuit to an external circuit while converting the signal level, that is, a device which converts the level of the signal supplied from inside of the LSI (large-scale integrated circuit) operated by the first power supply system in which the first supply potential VDD1 and grounding potential GND are supplied, and supplying to a device outside of the LSI operated by the second power supply system in which the second supply potential VDD2 and grounding potential GND are supplied.
The operation of this conventional semiconductor integrated circuit with signal level converting function is explained below. To begin with, the operation mode (input mode) of receiving a signal from the external circuit through the input-output terminal 3, and converting the signal level of the entered signal will be explained.
This input mode operates when the control signal IN2 becomes H level. By the control signal IN2 of this H level, the NMOS transistor MN113 is turned on, and the potential of the drain of the NMOS transistor MN113 drops to the grounding potential GND, and the PMOS transistor MP114 having the gate connected to its drain is turned on.
The inverter G112 outputs a signal of L level when it receives the control signal IN2 of H level, and hence the NMOS transistor MN114 having the gate connected to the output terminal of this inverter G112 is turned off. As a result, the PMOS transistor MP114 is turned on, and the potential of the node N112 rises to the second supply potential VDD2, so that the PMOS transistor MP113 is turned off. Thus, the node N112 becomes H level.
In this input mode state, when the data input signal IN1 becomes H level, the NMOS transistor MN111 is turned on, and the potential of the drain of the NMOS transistor MN111 declines to the grounding potential GND, thereby turning on the PMOS transistor MP112 having the gate connected to its drain.
At this point, the inverter G111 outputs a signal of L level when it receives a data input signal IN1 of H level, and therefore the NMOS transistor MN112 having the gate connected to the output terminal of this inverter G111 is turned off. Therefore, the potential at the node N111 raises to the second supply potential VDD2 as the PMOS transistor MP112 is turned on, and thereby the PMOS transistor MP111 is turned off. Thus, the node N111 also becomes H level.
On the other hand, when the data input signal IN1 becomes L level, the NMOS transistor MN111 is turned off, and the inverter G111 outputs a signal of H level when it receives a data input signal IN1 of L level, so that the NMOS transistor MN112 having the gate connected to the output terminal of this inverter G111 is turned on.
Consequently, the potential of the node N111 drops to the grounding potential GND and the PMOS transistor MP111 is turned on. Further, the potential of the drain of the PMOS transistor MP111 rises to the second supply potential VDD2. Therefore, the PMOS transistor MP112 is turned off, and consequently the node N111 becomes L level.
Accordingly, in the input mode, whether the data input signal IN1 is at L level or H level, as far as the control signal IN2 is at H level, the node N112 is at H level, and a signal of L level is input into one of the input terminals of the NAND gate G114 through the inverter G113. Therefore, the node N114, which is the output of the NAND gate G114, is H level, and the PMOS transistor MP115 is turned off.
In this case, a signal of H level is input into one of the input terminals of the NOR gate G115, and the node N115, which is the output of the NOR gate G115, becomes L level, and the NMOS transistor MN115 is turned off. Since both the PMOS transistor MP115 and NMOS transistor MN115 are turned off, the junction of the drain of the PMOS transistor MP115 and the drain of the NMOS transistor MN115 becomes a high impedance state with respect to the input-output terminal 3. Thus, the output buffer circuit 12h becomes a high impedance state with respect to the external circuit. Therefore, the signal from outside applied to the input-output terminal 3 is transmitted to the input buffer 9 without being spoiled.
The operation mode (output mode) for receiving the data input signal IN1 from the internal circuit and converting the signal level of the entered data input signal IN1 will now be explained. This output mode operates when the control signal IN2 becomes L level.
The NMOS transistor MN113 is turned off when it receives the control signal IN2 of L level. The inverter G112 outputs a signal of H level when it receives the control signal IN2 of L level. Therefore, the NMOS transistor MN114 having the gate connected to the output terminal of this inverter G112 is turned on.
As a result, the potential at the node N112 drops to the grounding potential GND, and the PMOS transistor MP113 is turned on. Further, the potential of the drain of the PMOS transistor MP113 raises to the second supply potential VDD2. Therefore, the PMOS transistor MP114 is turned off, and consequently, the node N112 becomes L level.
In this output mode state, when the data input signal IN1 becomes H level, the same as in the input mode mentioned above, the node N111 becomes H level. As a result, a signal of H level of the node N111 is entered in one of the input terminals of the NAND gate G114, and a signal of H level converted to the signal of L level of the node N112 is entered in other input terminal through the inverter G113, so that the node N114, which is the output of the NAND gate G114, becomes L level. Thus, the PMOS transistor MP115 is turned on.
In this case, the H level signal of the node N111 is fed into one input terminal of the NOR gate G115, and the L level signal of the node N112 is fed into other input terminal, so that the output of the NOR gate G115, that is, the node N115, becomes L level. Therefore, the NMOS transistor MN115 is turned off.
When the PMOS transistor MP115 is turned on and the NMOS transistor MN115 is turned off, the potential at the junction of the drain of the PMOS transistor MP115 and the drain of the NMOS transistor MN115 rises to the second supply potential VDD2. Therefore, the data input signal IN1 of H level of the first supply potential VDD1 is issued from the input-output terminal 3 as a signal of H level of the second supply potential VDD2.
In this output mode state, on the other hand, when the data input signal IN1 becomes L level, same as in the above case of input mode, the node N111 becomes L level. As a result, the L level signal of the node N111 is fed into one input terminal of the NAND gate G114, and the H level signal converted from the L level signal of the node N112 through the inverter G113 is fed into other input terminal, so that the node N114 which is the output of the NAND gate G114 becomes H level. Thus, the PMOS transistor MP115 is turned off.
In this case, the L level signal of the node N111 is fed into one input terminal of the NOR gate G115, and the L level signal of the node N112 is fed into other input terminal, and the node N115, which is the output of the NOR gate G115, becomes H level. Thus, the NMOS transistor MN115 is turned on.
When the PMOS transistor MP115 is turned off, and the NMOS transistor MN115 is turned on, the potential at the junction of the drain of the PMOS transistor MP115 and the drain of the NMOS transistor MN115 drops to the grounding potential GND. Therefore, the data input signal IN1 of L level of the internal circuit is output from the input-output terminal 3 as a signal of L level to the external circuit.
However, in such a conventional semiconductor integrated circuit with signal level converting function, so as not to lose the saving effect of power consumption by two power supplies for the signal level converting function of the input-output circuit, it is necessary to add a D type flip-flop circuit. In other words, it is necessary to provide a centralized control and not to disperse the input-output circuit inside the semiconductor circuit.
Therefore, it is necessary to provide a D type flip-flop circuit and connect this D type flip-flop circuit in the prior stage of the input-output circuit, when converting the level of the signal supplied from the internal circuit of the LSI operated by the first power source system (the power source system in which the first supply potential VDD1 and grounding potential GND are supplied), and after a certain time delay, issuing to the circuit outside of the LSI operated by the second power source system (the power source system in which the second supply potential VDD2 and grounding potential GND are supplied).
As explained above, in the conventional art, since the input-output circuit which actually converts the signal level and the D type flip-flop are not designed as independent circuit structures, in the entire semiconductor integrated circuit, the number of elements and their layout are not always efficient. Therefore, it is also a cause of lowering of input and output speed of the signal accompanied by level conversion.